In this course e-mail will be used as a means of communication with students. You will be responsible for checking your e-mail regularly for class work and announcements. The complete text of the University electronic mail notification policy and instructions for updating your e-mail address are available at Use of Canvas and Class Web SiteThis course uses the class web page and Canvas to distribute course materials, to communicate and collaborate online, to submit assignments and to post solutions and grades. You will be responsible for checking the class web page and the Canvas course site regularly for class work and announcements. As with all computer systems, there are occasional scheduled downtimes as well as unanticipated disruptions. Notification of disruptions will be posted on the Canvas login page. Scheduled downtimes are not an excuse for late work. However, if there is an unscheduled downtime for a significant period of time, I will make an adjustment if it occurs close to the due date. Students with disabilitiesThe University of Texas at Austin provides upon request appropriate academic accommodations for qualified students with disabilities. For more information, contact the Services for Students with Disabilities (SSD) at 471-6259, Religious HolidaysReligious holy days sometimes conflict with class and examination schedules. If you miss an examination, work assignment, or other project due to the observance of a religious holy day you will be given an opportunity to complete the work missed within a reasonable time after the absence. It is the policy of The University of Texas at Austin that you must notify each of your instructors at least fourteen days prior to the classes scheduled on dates you will be absent to observe a religious holy day. Classroom Evacuation and Emergency PreparednessAll occupants of university buildings are required to evacuate a building when a fire alarm and/ or an official announcement is made indicating a potentially dangerous situation within the building. Familiarize yourself with all exit doors of each classroom and building you may occupy. Remember that the nearest exit door may not be the one you used when entering the building. If you require assistance in evacuation, inform your instructor in writing during the first week of class. For evacuation in your classroom or building:Follow the instructions of faculty and teaching staff.Exit in an orderly fashion and assemble outside.Do not re-enter a building unless given instructions by emergency personnel.
The University of Texas at Austin Department of Electrical and Computer EngineeringEE 382M.7, VLSI I (Unique numbers 16675 --)EE 460R, Introduction to VLSI Design (Unique numbers 16460 --)Class meets Tu. Th. 12:30 - 2:00 pm, EER 1.516 INSTRUCTOR: Jacob A. Abraham Office: EER 4.874, Phone: (512) 471-8983 Office hours: Tu. Th. 11:00 - 12:30, in EER 4.874, or byappointment Zoom link for Office Hours: E-mail: Synchronous Lecture Delivery (see Canvas for recordings): ADDITIONAL DISCUSSION HOURS:Some Sundays, 1:00pm - 3:00pm, to be announced. There will be a zoom session, Sunday 8 November, 2 pm - 4 pm to answer anyquestions before the second exam. Textbook:CMOS VLSI Design by Weste and Harris, 4th edition,Addison-Wesley/Pearson, 2011.PREREQUISITES:Logic design, computer architecture.Students are expected to be able to design logic circuits andimplement state machines using logic and memory elements, and have an understanding of computer architecture.OUTLINE:This course covers all the aspects of design and synthesis of Very Large ScaleIntegrated (VLSI) chips using CMOS technology. Complex digital systems arebuilt using integrated circuit cells as building blocks and employinghierarchical design methods. Design issues at layout, schematic, logic andRTL levels will be studied. Commercial design software will be used forlaboratory exercises.The lectures will discuss the basics of digital CMOS design. Homeworkproblems will be assigned to reinforce the concepts discussed in class.Students are encouraged to work together on the homework problems, and mayturn in a single solution as a team. However, every member of the team shouldmake sure he or she thoroughly understands the problems, since this will helpin the exams. Homework is due week after it is assigned and should beuploaded on to Canvas (please remember to note the names of all the teamparticipants on the submission).Application of the concepts studied in class to larger designs will be donevia the computer-aided design laboratory exercises which are based on commonindustry design practice. Commercial tools and an open-source standard celllibrary are used for the labs. Laboratory exercises will enable students tolearn all aspects of digital design, including: layout of simple cells and thegeneration of larger blocks using these cells; designs at the schematic level,and the use of timing verification tools; the use of automatic place-and-routetools, and the concepts of post-layout timing closure; design at theregister-transfer level using the Verilog hardware description language; andthe use of synthesis tools to generate the design details with a standard celllibrary.There will be two in-class exams. All exams are open book and open notes.Several previous exams will be posted before the exam dates. The final examfor EE 460R will be on the date and location assigned by the registrar (seefinal exam schedule available about a month before the end of the semester).There is no final exam for graduate students; the team project replaces thefinal exam.Graduate students are also required todo a team project and submit the design details and results along with asummary report. The teams should work with the instructor and the TAsthroughout the semester on the project.TEACHING ASSISTANTSThere is one teaching assistant for the class. He will help you learn thetools needed to complete the laboratory exercises and gain furtherunderstanding of the topics in the class. Akib Shah Lab./discussion: Remote.Time slots: Piazza discussion forum LABORATORY:The laboratory exercises are key to understanding to designing VLSI circuitsin real life. Unfortunately, the commercial tools we use are very complicatedand require a steep learning curve to complete the laboratory exercises by thedeadlines. The TAs will hold demonstrations and discussion sessions in EER0.810, to help students learn the tools rapidly. Each student is enrolled ina specific lab session, but students are welcome to attend any session oftheir choice; however, please let the TAs know that you have changed thesession you are attending.Since it is very important to meet schedules in the real world, we willadd/subract points for the labs based on whether the submission is early orlate.Early submission: additional 5% points per day, maximum of 10%.Late submission: loss of 5% per day, maximum of 25%; submissions will not beaccepted more than 5 days late.DESIGN PROJECTGraduate students are required to design a VLSI subsystem as part of a team;this is in lieu of a final exam. The link above provides more information.Course Outline and Schedule (tentative)DATEDAYTOPIC OF LECTURE/DISCUSSIONReadingHOMEWORKLAB. ASSIGNMENTEXAMSAug. 27Thur.1. Introduction, CMOS Transistors1.1 - 1.3Homework 0 Lab. 1 Assigned Sep. 1Tue.2. CMOS Fabrication and Layout3.1 - 3.5 Sep. 3Thur.3. Implementing Logic in CMOS1.4 - 1.5Homework 1 Sep. 8Tue.4. MOS Transistor Theory2.1 - 2.3.1 Sep. 10Thur.5. CMOS Gate Characteristics2.3.2 - 2.6, 4.3 - 4.4Homework 2 Sep. 15Tue.6. Logical Effort4.3 - 4.5 Sep. 17Thur.7. Combinational Circuits9.2 - 9.2.1Homework 3 Sep. 22Tue.8. Design of Adders11.1 - 11.2 EE 382M: Lab. 1 Due/Lab. 2 Assigned Sep. 24Thur.9. Datapath Design11.3 - 11.10 Sep. 29Tue. 10. Interconnects in CMOS Technology10.1 - 10.4 Oct. 1Thur. Exam. 1Oct. 6Tue.11. Sequential Elements6.1 - 6.6Homework 4 EE 460R: Lab. 1 Due/Lab. 2 Assigned Oct. 8Thur.12. Dynamic CMOS Logic9.2.2 - 9.2.5, 9.4 - 9.5 Oct. 13Tue.13. Memories and PLAs12.1 - 12.7 Oct. 15Thur.14. Introduction to VerilogAppendix A Homework 5 EE 382M: Lab. 2 Due/Lab. 3 Assigned Oct. 20Tue.15. Nanoscale Design Issues2.4, 7.2 Oct. 22Thur.16. Circuit Design Pitfalls, Resilience7.3, 7.6, 9.3, Notes Oct. 27Tue.17. Design Verification15.1 - 15.4 Homework 6 Oct. 29Thur.18. Design for Low Power3.1 - 3.5 Nov. 3Tue.19. Introduction to Manufacturing Test15.5, Notes Homework 7 Nov. 5Thur.20. Design for Testability15.6, NotesEE 460R: Lab. 2 Due/Lab. 3 Assigned Nov. 10Tue.21. Skews, Scaling10.2, 10.5 - 10.9, 7.4 - 7.5 EE 382M: Lab. 3 Due Nov. 12Thur. Exam. 2Nov. 17 Tue.22. SOI Technology, Packaging9.5, 9.6, 13, 14.5 Nov. 19Thur.23. Future DirectionsNotes Nov. 24Tue.Project presentations Dec. 1Tue.Project presentations Dec. 3Thur.Project Presentations EE 460R: Lab. 3 due (December 5) Dec. 10Thur.9:00 am - 12:00 noon EE 460R: Final ExamGRADES:EE 382M:Homework 10%Exams I and II 30%Laboratory Exercises 45%Project 15%EE 460R:Homework 10%Exams I and II 25%Laboratory Exercises 45%Final Exam 20%
In the design cycle of a VLSI complexity integrated circuit (IC), the post-fabrication testing phase follows the design phase. Testing is an important phase during which our goal is to ensure that the circuit behaves the way it is expected to behave. A suite of test vectors and associated expected responses are used to test the IC. Though it looks like testing should be worried about post-fabrication, the designer, in fact, must ensure the circuit testability during the design phase rather than an after-thought. In this course, you will learn the entire gamut of digital system testing issues and solutions, namely, fault modeling, fault detection, development of test-suites, automation of test vector generation, etc. By completing this course, you will Gain a deep understanding of IC testing problem; Be able to analyze a given logic-level circuit for fault coverage; Be able to design and implement automatic test generation algorithms; and Gain knowledge on design-for-testability methods. 2b1af7f3a8